The maximum available memory address space for flash memory on the MC9S12DP256B is 1M byte (1024K bytes). Since the size of internal flash memory is only 256K, the other 768K would have to be implemented using external memory. A 20-bit address bus would be required to fetch instructions from external flash memory from the 1M address space. The MC9S12DP256B sends out a 20-bit address using the following ports:
A7-A0 from Port B
A13-A8 from Port A (bits 5 - 0 of Port A)
A19-14 from Port K (bits 5 - 0 of Port K)
If the MC9S12DP256B is presenting the following values on the pins listed below, at the time that it sends out a low-to-high transition on the ECLK pin, from which external memory location (or locations) is it trying to read from?

Lstrb* = 0 (The "*" indicates that this is a low-active signal.)
Port A = 82 hex
Port B = 40 hex
Port K5-0 = 100111 binary
R/W* = 1
(b) repeat for
Lstrb* = 1
Port A = 82 hex
Port B = 40 hex
Port K5-0 = 100111 binary
R/W* = 1
(c) repeat for
Lstrb* = 0
Port A = 82 hex
Port B = 41 hex
Port K = 100111 binary
R/W* = 1
(d) What should happen in the memory interface when a low to high transitionoccurs on the ECLK signal from the microcontroller?