Task Description
This task requires the designs simulation and physical implementation of a 4-bit ALU using the hardware description language Verilog with the finished design implemented upon an. Altera DE2-115 FPGA development board.
The envisaged design will be hierarchical, with some design elements provided direct from class notes, whilst others require modification and/or complete design.
To complete this task you will need to use Altera Quartus that is freely available to download (web pack version).
Specification
Your 4-bit ALU must be able to execute the instruction set shown in Table-1, below:
|
Operation
|
Instruction
|
Opcode
|
|
ACC = AUX (Load Accumulator)
|
LD
|
000
|
|
ACC = ACE + AUX (Add)
|
ADD
|
001
|
|
ACC = ACE - AUX (Subtract)
|
SUB
|
010
|
|
ACC = ACE & AUX (bit-wise And)
|
AND
|
011
|
|
ACC = ACE I AUX (bit-wise Or)
|
OR
|
100
|
|
ACC = ACC Λ AUX (bit-wise Exor)
|
EXOR
|
101
|
|
ACC = ACE >> 1 (Rotate right by 1 bit)
|
R5
|
110
|
|
ACC = ACE << 1 (Rotate left by 1 bit)
|
LS
|
111
|
Table-1
The ALU operands are provided by the accumulator (Acc, via acc_bus) and bus aux_bus. The output of each ALL) operation is stored in the accumulator; the value of the accumulator can also be updated direct y using LD (load) command.
The schematic design of the required ALL) and subsequent DE2-1 1 5 development board interface connections are shown in Figure 1, below,
All data path signals in the design are 4-bit unless otherwise stated. Register Acc is clocked by signal clk_reg, and reset by signal nClr (1-bit signals, not shown on diagram).
Attachment:- Assignment Files.rar