2.  Suppose that we modify the MIPS ISA by adding the lwro instruction. The lwro (load word - register offset) operates similar to regular lw instruction. However, the offset value comes from a third register instead of an immediate. The assembly format for the instruction is as follows:
lwro $r1, $r2 ($r3)
Where $r1 is destination register, $r3 is base and $r2 is offset. Note that this is exactly the same format as lw except that now a register is sitting in the place of the immediate.
a.  What type of MIPS instruction is best suited for encoding this instruction (R-type, I-type or J-type)?

R-type is best suited for this instruction because there are 3 registers being used, whereas if it were I-type, we would only need 2 registers and an immediate.

b. In a minimal design that imposes the minimum change to our single-cycle implementation, where is the best place to encode $r1, $r2 and $r3 in the instruction? i.e. which one is best suited to be $rs, $rt or $rd?

$rd would be $r1; $rs would be $r3; $rt would be $r2.

c.  Give the minimum changes - additions and/or deletions of hardware components (e.g., muxes) that need to be made to the single cycle MIPS datapath to accommodate this modification. (Give your answer with words such as "A mux is needed at the input of the RA1 of register file which selects between rs and rt. The control signal for this new mux is called NEW1." Note: this is not the correct answer! The answer can be as simple as "no change is needed" or as complicated as adding a few components.)

d.  Give the settings for the control signals to execute the modified instruction lwro. Use the keywords given to you for your answer. Use the last (blank) field to give the setting for any control signals that you had to add to the datapath in part c.