Suppose that a switch is designed to have both input and output FIFO buffering. As packets arrive on an input port they are inserted at the tail of the FIFO. The switch then tries to forward the packets at the head of each FIFO to the tail of the appropriate output FIFO.

(a) Explain under what circumstances such a switch can lose a packet destined for an output port whose FIFO is empty.

(b) What is this behavior called?

(c) Assuming the FIFO buffering memory can be redistributed freely, suggest a reshuffling of the buffers that avoids the above problem, and explain why it does so.