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Q1) Show the layout of the specified cache for a CPU that can address 8M x 16 of memory. Give the layout of the bits per location and the total number of locations.

a) The cache holds 128K x 16 of data and has the fully associative strategy

b) The cache holds 128K x 16 of data and has the direct mapped strategy

c) The cache holds 128K x 16 of data and has the two-way set-associative strategy.

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Computer Engineering, Engineering

Category:- Computer Engineering
Reference No.:- M9276953

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