Setting up a Xilinx project for the BCD Clock

Objective: This document is intended to be used as a reference guide to aid in setting up and working with a Xilinx ISE WebPACK project for use with the BCD clock project.

Project Initiation

1. Create a new Xilinx project as outlined in the "Introduction to Xilinx ISE.pdf" document.

2. Be sure that the XST (VHDL/Verilog) synthesis tool and the ISE simulator are selected as the default simulator for simulation purposes.

3. The project should be initiated with a top-level schematic

Design Entry

1. Regardless of the design entry method used for a particular system subsection (schematic capture or HDL) each subsystem will be integrated within a top-level schematic.

2. For Schematic Capture designs:

a. Design the individual subsystem schematic right on the top-level schematic page and then to cut and paste the design into an associated symbols schematic page or

b. Design the individual subsystem schematic in its already created symbol schematic page.

Symbol Creation

1. Select the schematic that the symbol is desired for from the "Hierarchy" window and then select the "Create Schematic Symbol" option from the "Design Utilities" window as shown in Figure 1.

a. Default symbol is created automatically once the "Process "Create Schematic Symbol" completed successfully" message is written to the "Console" window.

2. The newly created symbol can be selected for addition to any schematic by selecting the symbol from under the current project directory category as shown in Figure 2.

a. The newly added symbol can be edited by right-clicking on the symbol and selecting the "Edit Symbol" option under the "Symbol" category

i. The size and style of the symbol can be changed along with the pin layout

ii. It is recommended that the symbol inputs remain on the left, top, or bottom sides with the symbol outputs on the right side.

Figure 1: Creating a symbol for a selected schematic in Xilinx WebPACK

Figure 2: Selecting a created symbol for addition to a schematic

Subsystem Simulation

Most subsystems of the BCD clock need to be simulated to verify correct operation. When multiple design sources exist for a project, the simulation file must be associated with a single one or with the top-level schematic. There can therefore be multiple simulation files associated with a single project, each testing various subsystem designs. Refer to the document entitled "Digital Circuit Timing Analysis Using Xilinx ISE.pdf" for details on how to setup a simulation using the Xilinx ISE Simulator.