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Repeat Exercise 7.77 for the asymmetric BUT flop in Figure X7.78.

1781_1db2c901-a5ca-4fef-a9d3-e334239dcbf8.png

Exercise 7.77

A BUT flop may be constructed from an NBUT gate as shown in Figure X7 .77. (An NBUT gate is simply a BUT gate with inverted outputs; see for the definition of a BUT gate.) Analyze the BUT flop as a feedback sequential circuit and obtain excitation equations, transition table, and flow table. Is this circuit good for anything, or is it a flop?

1738_25373583-e6aa-4d65-b27f-b3b42a85c8d0.png

Computer Engineering, Engineering

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