Question: Timing Budget: You are designing a computer system using a technology with the properties shown in the Table. Your design calls for six gate delays (and intervening wires) during a clock cycle for intervening logic, and two gate delays plus driver, receiver, and wire delays for logic circuits that cross between two chips. No combinational circuits are allowed that involve three chips. What is the fastest clock rate you can safely (worst-case analysis) operate at using synchronous edge-triggered timing? How fast could you operate if you used synchronous level-sensitive timing? (Assume your combinational logic can be easily broken into roughly equal-sized units of three gate delays each.)
