Question no. 1 Write VHDL code for the LFSR circuit given in Fig 1. Use the sample entity statement shown in Fig 2. Use the testbench code given with assignment to test your VHDL code. (Note: For the D-flip-flop, make output node, Q goes to logic ‘1' or "high" when reset is at logic "1" or "high" and also if the name of the ports in the entity is different than the VHDL code shown in Fig 2, the testbench will not work).

Question no. 2 For the given state machine shown in Fig 3 write the VHDL code. Use the sample entity statement given in the question. Use the testbench code given with assignment to test your VHDL code. (Note: if the name of the ports in the entity is different than the VHDL code shown in Fig 4, the testbench will not work)

Attachment:- vhdl.zip