Question: A Faulty Synchronizer: A hapless engineer has designed a synchronizer using two flip-flops constructed from dynamic latches. The high-level schematic on the top shows asynchronous symbol x being sampled on the rising edge of the clock. After waiting a cycle for any metastable states to decay, the output of the first flip-flop is resampled by the second flip-flop to generate the synchronized output xs. As shown on the bottom, each flip-flop is really constructed as a pair of dynamic latches, giving four dynamic latches for the synchronizer as a whole. Given the numbers in Table 10-1, what is the probability of synchronization failure for this synchronizer? A more experienced engineer points out that the synchronizer can be greatly improved by changing just one of the four dynamic latches to a static latch. Which one does she suggest be changed? Why?