Question 1. (Dynamic Power and Energy) Suppose we developed a new, simpler processor A that has 85% of the capacitive load of the more complex, older processor B. Further, processor A has adjustable voltage so that it can reduce 15% of the voltage compared to processor B. As the result, it results in a 15% reduction in frequency for processor A. What is the impact on dynamic power? (i.e., how much power reduction can processor A achieve compared to processor B?)

Question 2. (Amdahl's Law) A computer system contains a special processor for doing floating- point operations. You have determined that 60% of the computations in a program can use the floating-point processor. When a program uses the floating-point processor, it runs 40% faster than when it does not use it.

a. What is the overall speedup by using the floating-point processor?

b. In order to further improve the speedup you are considering two options: Option 1: Modifying the compiler so that 70% of the computation in a program can use the floating-point processor. Cost of this option is $50K.

Option 2: Modifying the floating-point processor so that the speedup of the floating-point processor is 100% faster than when it does not use it. As a result of this modification, however, only 50% of the computation in a program can use the floating-point processor. Cost of this option is $60K.

Which option would you recommend? Justify your answer quantitatively.

Question 3. (Cache Organization) Given the following requirements for cache design for a 64-bit- address computer: (1) cache contains 64KB of data, and (2) each cache block contains 8 words. (A word in a 64-bit machine is 64 bits long).

a. If we adopt directly-mapped cache, what is the size of the tag field (in bits) in the address? What is the total size of the cache (in KB)?

b. If we adopt 8-way set-associative cache, what is the size of the tag field (in bits) in the address? What is the total size of the cache?

Question 4. (Average Memory Access Time) A processor is connected to the memory by an architecture composed of an L0 and an L1 cache. The access time of the L0 cache is 1 cycle, for the L1 cache it is 15 cycles, while for the memory 140 cycles. The local miss rate is 9% for the L0 cache and 2% for the L1 cache.

a. Compute the average memory access time (AMAT) of the processor.

b. What would be the AMAT if the L1 cache would not be present? How much does the L1 cache improve on the memory access time?

Question 5. (Decoding Machine Language)

a. What is the machine instruction (in hex form) for below assembly statement?

1w $t5, 1000($t3)

b. What is the assembly language statement corresponding to below machine instruction?

00af8020hex