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Problem

Consider the following pipelined processor with four stages. This pipeline has a total evaluation time of six clock cycles. All successor stages must be used after each clock cycle.

820_pipelined processor.jpg

(a) Specify the reservation table for this pipeline with six columns and four rows.

(b) List the set of forbidden latencies between task initiations.

(d) List all greedy cycles from the state diagram.

(e) What is the value of the minimal average latency?

(f) What is the maximal throughput of this pipeline?

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Computer Engineering, Engineering

Category:- Computer Engineering
Reference No.:- M92768792

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