Problemconsider the five-stage pipeline processor specified, Ask an Expert

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Problem

Consider the five-stage pipeline processor specified by the following reservation table:

668_reservation table.jpg

(a) List the set of forbidden latencies and the collision vector

(b) Draw a state transition diagram showing all possible initial sequences (cycles) without causing a collision in the pipeline.

(d) Identify the greedy cycles among the simple cycles.

(e) What is the minimum average latency (MAL) of this pipeline?

(f) What is the minimum allowed constant cycle in using this pipeline?

(g) What will be the maximum throughput of this pipeline?

(h) What will be the throughput if the minimum constant cycle is used?

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Computer Engineering, Engineering

Category:- Computer Engineering
Reference No.:- M92768790

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