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Problem

Aerostation uses 1.5 GHZ processor with a claimed 1030-HIPS rating to execute a given program mix assume a one-cycle delay for each memory access.

{a} What is the effective CPI of this computer?

{b} Suppose the processor is being upgraded with a 3.0 GHZ clod-t. However. even with faster cache, two clock cycles are needed per memory access. If 30% of the instructions require one memory access and another 5% require two memory accesses per instruction. what is the performance of the upgraded processor with a compatible instruction set and equal instruction counts in the given program mix?

 

Computer Engineering, Engineering

  • Category:- Computer Engineering
  • Reference No.:- M92768744

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