Problem : Design of a 4-bit Magnitude Comparator

Design, simulate and verify a 4-bit magnitude comparator in Verilog. Use a variety of inputs to test your design and include the results in your report.

You may approach this problem in a hierarchical fashion.

If you do so, first design a single-bit comparator and then wire four copies of the same comparator appropriately to produce a 4-bit comparator.

A single bit comparator circuit has two data inputs, three control inputs and three compare outputs.

The three control inputs provide a mechanism for generation of multi-bit comparators by cascading several 1-bit comparators. This is how the single bit comparator logic works.

The A>B output is 1 if "the A input is greater than the B input (AB is 10)" or if "A is equal to B and the > input is 1." The A=B output is 1 if "A is equal to B and the = input is 1."

The A < B output is the opposite of the A>B output. This line becomes 1 if "A input is less than B output (AB is 01)" or if "A is equal to B and the < input is 1."

Based on this functional description of the 1-bit comparator, Karnaugh maps for its three outputs can be extracted easily. Since the logic is simple, you really don't need to refer to any literature other than the Verilog manual for its implementation.

However, if you need any help, you could look at any elementary books on Logic Design.

If you have any difficulty in understanding this problem, you may first consider a few simple numbers and make comparisons starting at the lsb moving toward the msb.

If you like to take a "flat design" approach instead of the hierarchical design paradigm (that is, consider the 4-bit comparator as a single module), such a solution is also acceptable.

But in practice, you generally follow a modular/hierarchical design approach.