Please answer this five questions:

Use the following code fragment. Write all assumptions you make regarding hardware.

Loop: LD R1,0(R2) ;load R1 from address 0+R2

DADDI R1,R1,#1 ;R1=R1+1

SD R1,0,(R2) ;store R1 at address 0+R2

DADDI R2,R2,#4 ;R2=R2+4

DSUB R4,R3,R2 ;R4=R3-R2

BNEZ R4,Loop ;branch to Loop if R4!=0

Assume that the initial value of R3 is R2 + 396

1. Data hazards are caused by data dependences in the code. Whether a dependency causes a hazard depends on the machine implementa- tion (i.e., number of pipeline stages). List all of the data dependences in the code above.

Record the register, source instruction, and destination instruc- tion; for example, there is a data dependency for register R1 from the LD to the DADDI.

2. Show the timing of this instruction sequence for the 5-stage RISC pipeline without any forwarding or bypassing hardware but assuming that a register read and a write in the same clock cycle "forwards" through the register file, as we used in class. Assume that the branch is handled by flushing the pipeline. If all memory references take 1 cycle, how many cycles does this loop take to execute?

3. Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding and bypassing hardware. Assume that the branch is handled by predicting it as not taken. If all memory references take 1 cycle, how many cycles does this loop take to execute?

4. Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding and bypassing hardware. Assume that the branch is handled by predicting it as taken. If all memory references take 1 cycle, how many cycles does this loop take to execute?

5. High-performance processors have very deep pipelines-more than 15 stages. Imagine that you have a 10-stage pipeline in which every stage of the 5-stage pipeline has been split in two.

The only catch is that, for data forwarding, data are forwarded from the end of a pair of stages to the beginning of the two stages where they are needed.

For example, data are forwarded from the output of the second execute stage to the input of the first execute stage, still causing a 1-cycle delay.

Show the timing of this instruction sequence for the 10-stage RISC pipeline with full forwarding and bypassing hardware. Assume that the branch is handled by predicting it as taken. If all memory references take 1 cycle, how many cycles does this loop take to execute?