Consider the following computer: - 3 GHz, instruction buffers that essentially negate instruction load penalties, and the computer leaves writes to the cache negating write penalty. - 32Kb L1 Data cache, 90ps access (per word), 8 word blocks, 4-way associative, write-through, 1% miss ratio - connection bus (to L2): 2 words wide - 1Mb L2 cache, 5ns access, 32 word blocks, 4-way associative, write-back, 20% miss ratio 16.7% (1/6) dirty - connection bus to RAM: 4 words wide - 1Gb RAM, 55ns access, 5ns per word burst rate (repeat access from consecutive addresses) For this computer calculate the following: (a) What is the L2 read miss penalty? (b) What is the L1 read miss penalty? (c) What is the read penalty (L1 and L2 cache)? (d) Assume 33% (1/3) loads, and everything else is ideal. What is the CPI? (e) What would the CPI be if L2 cache was removed (i.e. redo the above without L2 cache, the bus from L1 to RAM is 2 words wide)? (f) What is the speedup of the system with L2 cache?