problem1. Assume that the meaning of the BUN instruction of the Basic Computer is changed to implement relative addressing mode, that is, PC <- PC + AR instead of PC<- AR.
a) prepare an optimal operation sequence to implement the new version, but make sure that the value of AC is not changed at the end of your implementation.
b) Is it probable to prepare an operation sequence to implement new version such that, at the end of the implementation, the values AC and DR are unchanged? If yes, prepare such an optimal sequence. Otherwise justify why it is not possible.
problem2. prepare the optimal sequence of control microinstruction to implement the following register transfer:
x: AR<- AR +DR, DR <- DR + 1
Your solution must use the minimum number of cycles and it should leave AC unchanged:
You might assume that AC contains an 11-bit quantity.
problem3. Archie Tecture has to prepare Basic Computer code that contains lots of "spinning loops" of the form:
Loop: ISZ A
He thinks that all his "spinning loops" will run faster if he reimplements them once he makes the following changes to the basic computer.
-Add a register to the bus system CTR (count register) to be selected with S1=0
-Replace the ISZ instruction with an instruction that loads a value into CTR:
LDC Address CTR<- M[Address]
- Add a register reference instruction ICSZ with the semantics: Increment CTR and skip next instruction if zero.
Answer the following:
a) Using as a model table 5-6, prepare the register transfer statements for the new instruction ICSZ and LDC
b) Is Archie correct assuming that all his "spinning loops" will run faster once he reimplements them using the next instruction? Justify carefully your answer.
problem4. Most machines have a shift left unit attached to the ALU. Using 4x1multiplexors and D-flip-flops, design a 4-bit shifter that accommodates these four operations: no shift, Circular shift left, logical shift right, and Circular shift right. The most significant bit is the sign bit.