Mips uses word alignment so all words are stored in memory, Ask an Expert

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Assume we modify the 8 block direct-mapped cache design to implement an 8-block 2-way set associa - tive cache.

(a) How many sets will there be?

(b) How many blocks will there be per set?

(c) MIPS uses word alignment, so all words are stored in memory on word boundaries; this means that address bits A[1:0] are always 00. How many and which address bits would be allocated for the set index?

(d) How many and which address bits would be allocated for the tag?

(e) What is the total size of the cache in bit?

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Computer Engineering, Engineering

Category:- Computer Engineering
Reference No.:- M9453705

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