Mini Project

Design of Dynamic RAM Controller

Design a simplified and shared dynamic RAM controller circuit which has the following specifications:

The inputs to the circuit are a 20 bit address (ADDRIN), a read signal (RD), a write signal (WR), and an enable signal (ALE). This circuit does not function until ALE becomes 1, then the 20-bit ADDRIN is loaded in as a row address (upper 9 t0 17) and a column address (0 to 8) bit registers. Also Read and Write, address line 18 (B0) and 19 (B1) signals are "stored". Subsequently, the row address is outputted at (ADDROUT) along with the row address strobe (RAS) signal (active low) which is generated one clock cycle later. The RAS (active low) signal is outputted according to rules in table 1. Then, the column address is outputted along with the column address strobe signal (CAS), which is generated one clock cycle later. Finally, if the operation is a write operation ( RD = 0, WR = 1), then the WE output is 1.Otherwise for a read operation ( RD = 1, WR = 0), the WE output remains 0. The controller returns to the initial state after generating all the required signals.

Your submission should include

1. A technical paper report written using IEEE format (refer to attached paper for guidelines). This paper should discuss the design DRAM controllers strategies, types and relate it to the internal structure of the DRAMs.( you need to research this and summarize the technical information and compare this design to other strategies)

2. The paper should have an appendix which includes

? Source code and test bench files along with waveforms & comments added to verify the functionality of design.

? Synthesis results and the estimated maximum speed of the circuit using 3 different state assignment methods.