Q1. Illustrate the hardware implementation of a logic circuit which uses logic gates and produces AND, OR, XOR, complement micro-operations (one signal at a time). The choice is to be based on the two input binary signals.
Q2. prepare down the steps comprised in memory read operation.
Q3. Describe with illustration a two address instruction format.
Q4. describe how DRAM refresh is implemented?
Q5. Where is cache situated in the computer? describe what cache hit is and cache miss?
Q6. What do you mean by prepare back policy?
Q7. Illustrate the meaning of Polling in Input-Output subsystem design?