(Hardware Description Languages) Write a Verilog module that describes the circuit of Exercise 3.26.

Exercise 3.26

(Design Problem) Consider a combinational logic subsystem that performs a 2-bit addition function. It has two 2-bit inputs, AB and CD, and forms the 3-bit sum, XYZ.

(a) Draw the truth tables for X, Y, and Z.

(b) Minimize the functions using 4-variable K-maps to derive minimized sum-of-products forms.

(c) In this chapter, we have introduced the full-adder circuit. What is the relative performance to compute the resulting sum bits of the 2-bit adder compared to two full adders connected together? (Hint: Which has the worst delay in terms of gates to pass through between the inputs and the final outputs, and how many gates is this?)