Fundamentals of Computer Systems Project - Huffman Decoder with Cache
1. Specification
Your objective is to design a cache for the Huffman Decoder from P3. The tree is encoded exactly as in the previous assignment. The only change here is that the TREE ROM is now a SLOW TREE ROM. It accepts addresses via a latency insensitive channel and, ten cycles later, provides the corresponding data.
Interface The HUFFDEC module has four latency insensitive interfaces:
- X is one bit wide and streams encoded bits from the test harness to HUFFDEC,
- CHAR is 8 bits wide and streams decoded characters out of HUFFDEC to the test harness,
- ADDR is 8 bits wide and streams addresses from HUFFDEC to SLOW TREE ROM,
- DATA is 17 bits wide and streams read data from SLOW TREE ROM to HUFFDEC.
Baseline Design The baseline design is provided in the scaffolding. It functions with the SLOW TREE ROM, but makes no attempts at caching the data extracted from the slow memory.
2. Test Harness
The test harness is identical to that of P5, except that latency mode has been removed. Note the original interface to HUFFDEC. Your submission must match this exactly.
3. Workloads
Huffman codes are based on character frequency, using short codewords for frequent characters and longer codewords for infrequent characters. The trees we will use are not laid out in memory with any eye towards locality. Each workload consists of a tree and set of characters, with the characters following a uniform random distribution. The workload provided in the scaffolding includes the same tree as in P3 and a sequence of 100 characters to decode.
Attachment:- Assignment File.rar