(Answered) For a direct-mapped cache design with a 32-bit address the

Engineering

For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache.

Tag 31-12

Index 11-6

Offset 5-0

a. What is the cache block size (in words)?

b. How many entries does this cache have?

c. What is the ratio between total bits required for such a cache implementation over the data storage bits?

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