A RISC machine may do both a mapping of symbolic registers to actual registers and a rearrangement of instructions for pipeline efficiency. An interesting question arises a to the order in which these operations should be done. Consider the following program fragment:
LD SR1, A
LD SR2, B
ADD SR3, SR1, SR2
LD SR4, C
LD SR5, D
ADD SR6, SR4, SR5

First do the register mapping and then any possible instruction reordering. How many machine registers are used? Has there been any pipeline improvement?
Starting with the original program, now do the instruction reordering and then any possible mapping. How many machine registers are used? Has there been any pipeline improvement?