Event-based Simulator

Digital  Logic  Simulation  method  sacrifices  performance  for  rich  functionality:  each active signal  is  calculated  for  every  device  it  propagates  through  during  a  clock  cycle.  Full  Event-based simulators  support  4-28  states;  simulation  of  Behavioral  HDL,  RTL  HDL,  gate,  and  transistor representations;  full  timing  calculations  for  all  devices;  and  full  HDL  standard.  Event-based simulators are like a Swiss Army knife with several different features however none are particularly fast.