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Design floating point arithmetic unit using VHDL (Block diagram and flowchart)

You need to prepare the drawing of the block diagram and flowchart with explanation for each of them for this project

"Design floating point arithmetic unit using VHDL"

Project Objectives

- To read32 bit input

- To achieve IEEE 754 floating point with sign bit: exponent and Mantissa

- Simulation results using Isim

- Pipelined Multiplied Multiplication, Rounding Exponent and square root operation

- Application on XILX FPGA

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Computer Engineering, Engineering

Category:- Computer Engineering
Reference No.:- M92185347
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