Design a circuit that meets the specifications of Exercise 7.89 using edgetriggered D flip-flops (74x74) and NANO and NOR gates without feedback loops. Give a complete circuit diagram and a word description of how your circuit achieves the desired behavior.

Exercise 7.89

Design a fundamental-mode flow table for a circuit with two inputs, EN and CLKIN, and a single output, CLKOUT, with the following behavior. A clock period is defined to be the interval between successive rising edges of CLKIN. If EN is asserted during an entire given clock period, then CLKOUT should be "on" during the next clock period; that is, it should be identical to CLKIN. If EN is negated during an entire given clock period, then CLKOUT should be "off' (constant I) during the next clock period. If EN is both asserted and negated during a given clock pe1iod, then CLKOUT should be on in the next period if it had been off, and off if it had been on. After writing the fundamental-mode flow table, reduce it by combining "compatible" states if possible.