Design a 4-bit shift register and design the up-counter. The shift register should have two control inputs, C1 and C0. When both inputs are 0, hold contents of the shift register in place. When C0 = 1, load new data into the shift register. When C1 = 1, Shift the contents of the shift register to the right, i.e. QB => QA, 0 => QD. When both inputs = 1, Shift the contents of the shift register to the left, i.e. QA => QB, 0 => QA.

Describe the inputs to the multiplexers for each of the four bits. For example, what are the multiplexer inputs for the C (third) bit of the shift register?