Consider a dynamic version of the ROM in Fig. in which the gates of the PMOS devices are connected to a precharge control signal φ. Let all the NMOS devices have W/L =3μm/1.2μmand all the PMO Sdevices haveW/L =12 μm/1.2μm. Assume k1n =3k1p =90μA/V2,Vtn =-Vtp =1 V, and VDD =5 V.
(a) During the precharge interval, φ is lowered to 0 V. Estimate the time required to charge a bit line from 0 to 5 V. Use as an average charging current the current supplied by a PMOS transistor at a bit-line voltage halfway through the excursion of 0 to 5 V (i.e., 2.5 V). The bit-line capacitance is 1 pF. Note that all NMOS transistors are cut off at this time.
(b) After the precharge interval is completed and φ returns to VDD, the row decoder raises the voltage of the selected word line. Because of the finite resistance and capacitance of the word line, the voltage rises exponentially toward VDD. If the resistance of each of the polysilicon word lines is 5 kΩ and the capacitance between the word line and ground is 2 pF, what is the (10% to 90%) rise time of the word-line voltage? What is the voltage reached at the end of one time constant?
(c) If we approximate the exponential rise of the word-line voltage by a step equal to the voltage reached in one time constant, find the interval ?t required for an NMOS transistor to discharge the bit line and lower its voltage by 1 V.
