C4-1. use an FPGA to implement the following Boolean equation:

X = AB.

(a) Create a Block Design File called prob_c4_1.bdf to define the logic circuit.

(b) Create a Vector Waveform File called prob_c4_1.vwf to test the operation of your design by showing the output waveform for all possible input conditions.

(c) Build a truth table for the Boolean equation.

(d) Download the design to the FPGA on your programmer board and demonstrate its operation by monitoring the output LED as you step through all switch combinations shown in your truth table from part (c).

part (c).

C4-2. Use an FPGA to implement the following B an equation:

X=AB+AB.

(a) Create a Block Design File called prob_c4_2.bdf to de ..:e the logic circuit.

(b) Create a Vector Waveform File called prob_c4_2.vwf to test the operation of your design by showing the output waveform for all possible input conditions.

(c)  Build a truth table for the Boolean equation.

(d) Download the design to the FPGA on your programmer board and demonstrate its operation by monitoring the output LED as you part (c).

step through all switch combinations shown in your truth table from

X Ai3C.

C4-3. Use an FPGA to implement the following Boolean equation:

(a) Create a Rinnly n 

Section 4-1

4-1. How does programmable logic differ from discrete digital logic lik_e the 7400 series?

4-2. What are two common ways to configure or define logic to PLD pro­gramming software?

4-3. What does HDL stand for in the acronym VHDL?

4-4. List the six steps in the PLD design flow.

4-5. How many different ICs would it take to implement the following equations?

(a)X = AB + BC

(b)Y = AB + BC + C + D

4-6. How is pin I identified in the PLCC package style used for the PLD in Figure 4-4?

4-7. What is the purpose of the PLD programmer boards shown in Figure 4-5?

Section 4-2

4-8. How many product terms are in the following equations?

(a)   X = AE^. + BC + Ac

(b)   Y = ABC + BC

(c)   Z = ABC + ACD + BCD

4-9. How does a PLA differ from a PAL?

4-10. Redraw the PLA circuitry of Figure 4-8 to implement the following

SOP equations:

(a)  X = AB + A B + AB

(b) Y = AB + AB

4-11. Why is it advantageous to use a CPLD or ASIC that is nonvolatile?

4-12. Refer to the data sheets in Appendix B (or the manufacturer's Web site) to determine the number of usable gates and macrocells in each of the following CPLDs:

(a)    Altera MAX EPM7128S

(b)    Xilinx XC95108

4-13. Instead of interconnecting logic gates, the FPGA solves its logic re­quirements by using what method?

4-14. Draw a 2-input look-up table (LUT) similar to Figure 4-11(b) for the equation X = A B + Ali.

4-15. Because most FPGAs are volatile, what must be done each time they are powered up?

Section 4-3

4-16. What are the two most common methods of design entry for FPGA development software?

4-17. What is the function of the compiler in FPGA development soft­ware?

4-18. What is the purpose of the three pin stubs in the bdf file shown in Figure 4- I 3(a)?

4-19. VHDL allows the user to enter the logic design via a ______________

editor.

4-20. Define the purpose of the following three VHDL program segments:

(a)   Library

(b)   Entity

(c)  Architecture

4-21. Write the VHDL entity declare for a three-input AND gate.

4-22. Write the VHDL archKeciire for a three art)! AND gate.

4-23. Draw the logic circuit to he implemented by the following VHDL architecture body:

ARCHITECTURE arc OF p4_23 IS

BEGIN

x < = (a AND (b OR c)):

y < = (a OR NOT b) AND NOT (b AND c):

z < = NOT (b AND c) OR NOT (a OR c):

END arc: