Consider a pipelined processor in which instruction memory can be accessed in one cycle (IFETCH stage), but data memory access takes two cycles (which can be labeled as stages MEM1 and MEM2). Assume 30% of instructions are loads, and that half (50%) of the loaded values are used in the cycle that immediately follows the load. Another quarter (25%) of the loaded values are used in the second cycle after the load instruction. Assume that there are no other hazards that require stalling. Compute the CPI of the above processor with the given workload.