Assume that the current value of PC=100H, and there are the following instructions resident in the memory, which are stored on four consecutive locations 100H, 101H 103, and 104Hin:
1- Load [2000H]
2- Add [2000H] ( Op-code = 01111)
2-Stor [2000H] (Op-Code= 01100)
3-Branch [1000H] (OP-code=01010)
1- Using the information in part a(BELOW), show the exact format for the above instruction and show how they are stored in the memory in terms of binary bits and how many flip flops are needed and the type of each one (latch, or rising or falling edge trigged) and why? 2- Show how many clock cycles are needed to execute each instruction and what is the total clock cycles that are needed to execute all of them.
3- If the memory, locations 2000H contains the data (00055H) on it, use the controller state diagram constructed in class to draw a table showing what are the content of PC, AC, MAR, MBR [100H], 2000H in each and every clock cycle ( fetch and execute cycles for all four instructions the instructions).
4- Show the data path building blocks (buses, Muxes, registers etc) that are needed to connect AC as a first source and MBR as a second source to all 8-ALU units and show the required control signals for selecting each ALU unit.
5- Assume that ALU code for Add is (111), use the state diagram for add instruction (fetch and execute cycles ) to show the timing diagram for the all output signals generated by the controller for only the second instruction, (Add [2000H] )
6- Use 5 to show why PC, AC, MAR, MBR to be designed ad latch, or rising or falling edge trigged? Justify your answer!
7- Use the one- Hot controller concept explained in class to show the D flip flop for the Branch [1000H] instruction.
What is the word size?
How that will affect the size of ALU and internal registers including PC, AC, MAR and MBR?
Draw a general model for the computer system showing how memory and CPU interact with each other. Show the necessary buses and signals that can be used for the communication between CPU and Memory, according to Von Neumann's architecture, and the width of each one.
How many instructions that this processor can support.