Assignment
Design an expandable 2-bit magnitude comparator that can be used as shown below. Use a behavioral dataflow description to create an expandable two-bit comparator from your Project 1 dataflow description for a 2-bit (non expandable) comparator. You do not need to draw a schematic. The equations do not need to be minimal. Note that A[3] is the MSB of A[3:0].
Create a testbench to exhaustively test your expandable 2-bit comparator then create a Verilog model of an 8-bit comparator using multiple connected instances of the tested 2-bit expandable comparator from above. Use the testbench from the course web site to test it. Note how the testbench instantiates the 8-bit comparator so that your module defines the ports correctly!
module Compare8Bit (A, B, IEQ, ILT, IGT, OEQ, OLT, OGT);
input [7:0] A, B;
input IEQ, ILT, IGT;
output OEQ, OLT, OGT;
Your Verilog programs must be compiled and simulated. Save and print the simulator timing diagrams (except for the 8-bit comparator) so that you can include it in your final report.
This final report must include:
1. A brief problem description
a. The problem your circuit solves
b. Specific requirements
2. The project deliverables (exactly what you are generating)
3. Approach/methodology (the steps you will take to solve the problem)
4. Your design work
5. Verilog source code listings (for all designs and their testbenches)
6. Timing diagrams showing how your 2-bit designs performed
7. Show the simulation output produced by my testbench for your 8-bit model but do NOT submit the timing diagram from simulating the 8-bit model.