Activity # 1 Initial study

1. List the instructions that require a result from the ALU and all of the remaining instructions.

Require result from ALU:                          Do not require result from ALU:

2. There are some instructions where the ALU and register_AC together will act as an accumulator. What is an accumulator?

3. There are some instructions that do not require an output from the ALU. You can choose the output of the ALU in these cases. What is it and why did you select it?

4. What are the input and output signals of the ALU entity and how many bits are they? Include an "A" to indicate the left input and a "B" to indicate the right input. Otherwise, you may choose names.

Inputs:                                        Outputs:

5. Choose four test cases and determine the correct output for each instruction that involves the ALU. Use hexadecimal. The test cases should verify the correct operation of each opcode as well as illustrate that connections are correct (correct bus numbering).

All inputs and all outputs should be ‘0' and ‘1' in at least one test case for one instruction. For the ADDI instruction, test the carry from LSB to MSB and proper sign extension of the address input. Note: this is a ridiculously low number of test cases. Many more would be included in a real design.

Activity #2 VHDL Code Simulations

Using the results from Activity #1, create the entity and architecture of the µP3 ALU. The VHDL code below has an outline of the code.
Create a new project lab3 with revision alu_tb_sim. Create a new VHDL file by selecting File > New... then clicking on VHDL File, then OK. Enter the following text. Be careful of punctuation. Use generic parameters to indicate the size of busses, using the default value
for this architecture.
-- alu.vhd
-- Implements the arithmetic and logical instructions
-- for the uP3 microprocessor
--
-- Author: Your name here, NAU EE
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity alu is
generic (
-- put generic parameter list here
);
port (
-- put port list here, use type SIGNED
);
end alu;
architecture behav of alu is
begin
process() -- include necessary signals in sensitivity list
begin
-- your code here!
end process;
end behav;

Create a symbol for this VHDL design. Use File > Create / Update > Create Symbol Files for Current File. Insert the symbol in the alu_tb_sim.bdf file.

There is VHDL and symbol file for opcode_gen on vista. The opcode generator is an 8 bit counter with positive-edge triggered clock and active high, asynchronous reset.

Place input and output pins in the bdf file and connect them to the symbol, using names of your choosing. Since this is only for simulation (and not for programming the DE1 board), you can choose names that indicate the function. Use the hexadecimal outputs as much as possible. You can make these "vector" pins using the syntax signal_name[7..0]. This is equivalent to the VHDL vector range 7 downto 0.
Make the alu_tb_sim.bdf entity the top-level entity. If you don't make it the top-level entity, it won't compile. Forgetting this can lead to a lot of lost time. Include all other necessary files and no others. Compile the design.

Create a force file to test the design. Use the four test cases from above and simulate them for each instruction. Do a functional simulation and verify that the results match the expected results from Activity #1. Display all of the input and output signals in hexadecimal
in the wave window. Here are some additional force file hints:

• The force file can have a .txt extension so that it will open in Notepad automatically.

• You can specify the time that a signal takes on a value relative to the current simulation time. If the current simulation time is 200ns, these commands will set reset to 0 at 200ns and then a pulse of width 50ns beginning at 1400ns.

force reset 0
force reset 1 1200ns
force reset 0 1250ns

• You can specify values in hex.

force in_A x"FFFF" 1200ns
Activity #3 Demonstration

You must have the simulation completed before the demo. The DE1 board will not accommodate all the inputs and outputs of the ALU so you will create another test bench for the demo. Use the test bench alu_tb_demo.bdf. You will need to edit this file. Note how you can label the names of busses (right click on the wire and edit Properties). Use the hexadecimal output from Lab #2 to display the important information for this demonstration. Program the FPGA target and test all instructions with all test cases.

Activity #4 Counter

The file TUTOR2.sof in bblearn contains a programming file for the DE1 board with two counters with asynchronous reset and clocks. Download this file onto the DE1 board and experimentally determine the function of all DE1 board inputs and outputs.

Comment on the effect of using a key versus a switch for the clock input and explain why there is a difference on the DE1 board.