(Answered) A program runs on a superscalar processor with a 2 ghz

Engineering

A program runs on a superscalar processor with a 2 GHz clock rate within a NUMA (non-uniform memory access) system. The number of instructions executed in the program is IC. The superscalar processor achieves an IPC (instructions per cycle) rating of 2 for instructions that do not reference remote memory. Each instruction that does reference remote memory incurs an additional 200 ns penalty over those that do not reference remote memory. The percentage of program instructions that access remote memory is 0.2%. What speedup would be achieved for the program if the remote memory access penalty could somehow be reduced to 10 ns per access?

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