A particular version of the regenerative sense amplifier of Fig. 16.20 in a 0.13-μmtechnology uses transistors for which /Vt / =0.4 V, k1n =4k1p =500 μA/V2, VDD =1.2 V, with (W/L)n =0.26 μm/0.13 μm and (W/L)p =1.04 μm/0.13 μm. For each inverter, find the value of Gm. For a bit-line capacitance of 0.4 pF, and a delay until an output of 0.9VDD is reached of 1 ns, find the initial difference voltage required between the two bit lines. If the time can be relaxed by 1 ns, what input signal can be handled? With the increased delay time and with the input signal at the original level, by what percentage can the bit-line capacitance, and correspondingly the bit-line length, be increased? If the delay time requiredfor the bit-line capacitances to charge by the constant current available from the storage cell, and thus develop the difference-voltage signal needed by the sense amplifier, was 2 ns, what does it increase to when longer lines are used?
