(a) Draw a block diagram for a parallel divider that is capable of dividing a positive 6-bit binary number by a positive 4-bit binary number to give a 2-bit quotient. Use a dividend register, a divisor register, a subtracter-comparator block, and a controlblock.

(b) Draw a state graph for the control circuit. Assume that the start signal St remains 1for one or more clock times after the division is complete, and St must be set to o to reset the circuit.

(c) Show how the subtracter-comparator could be realized using full adders and inverters.

(d) Show the contents of the registers and the value of C after each time step if initially the dividend is 101101and the divisor is 1101.