(a) Create a behavioral HDL description of t11e high-level state machine for the cycles-high counter of Example 5. 1.

(b) Create a test bench and simulate the system for some sample input sequences and verify correct behavior.

(c) Create a structural HDL description for the data path of the cycles-high corner in Figure 5.16(d).

(d) Create a controller FSM and connect it to the data path as in Figure 5.16(d).

(e) Use the earlier test bench to simulate the controller/data path system to verify correct behavior.