1. Draw a module that can accept a new value every cycle, enabling full throughput. You are not allowed to have any combinational paths from the downstream interface to the upstream interface (or vice versa). You will need two registers to store the incoming data.
2. Music player: input song. In the music player specification and simple block diagram (below), add the ability to input a song file into the RAM.
3. Assume that a module has a latency of 20 ns and that treg = 500 ps. Including the output register, what are the latency and throughput of this module when pipelined into five equal stages and then this pipeline is replicated five times.
4. Determine the state equations for the following FSM. The state, S, is the value at the top of each state while the output, o, is at the bottom of each state. The input signals are a and rst. Assume the R = 0, M = 6, and L=7. Show your Karnaugh maps. Ignore hazards.
Let S = ( s2, s1, s0 ) be the current state and N = ( n2, n1, n0 ) be the next state.
5. Compute tdGQ for the latch (below) in terms of the delays of the individual gates. Assume that the delay of gate Ui is ti.
6. For flip-flops with ts = 20, th = 10, tcCQ = 10, and tdCQ = 20 in a 1 GHz circuit, for any block of logic that separates two flip-flops, what is the minimum tc and maximum td?
7. Modify the divide-by-3 counter (below) to be a divide-by-4 counter.
8. Memory Addressing: For each of the following memories, state how many bits are needed to address the full capacity. Also explain which bits are used for byte, bank, and word selection. Assume byte addressing and that the bank selection is done with the bits just after the byte selection bits.
a) One array with 2,000 32-bit words.
b) Eight bit-sliced arrays, each with 1,000 16-bit words.
c) 16 banked arrays, each with 512 128-bit words.
d) Eight banks of 16 bit-sliced arrays, each array has 1,000 64-bit words.
9. What is the maximum initial voltage difference for a metastable system to settle to ΔV = 1 V within 7τs?
10. Calculate the mean time to failure of a system with fa= 200 MHz, fcy = 2 GHz, waiting one cycle for synchronization. Use the flip-flop parameters: ts = 50 ps, th = 20 ps, τs = 40 ps, and tdCQ = 20 ps.