(Answered) 1 assume 32 bit memory addresses which are word addresses

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1. Assume 32 bit memory addresses, which are word addresses. You have a direct-mapped cache with a block sizeof 4 words, and a size of 32 blocks. How many bits will the index, block offset, and tag be? How many total bits are required for the cache, including the data?

2. Assume 32 bit memory addresses, which are word addresses. You have a 4-way cache with a block size of 2 words,and a size of 16 blocks. How many bits will the index, block offset, and tag be? How many total bits are required for the cache, including the data?

3. Assume you have an instruction cache miss rate of 4%, and a data cache miss rate of 2%. The miss penalty is 100 cycles. You have a program that is 25% load-store instructions, with a base CPI of 1. What will its CPI be including cache misses?

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