Implementing FPGA Handshaking System Objectives

This project will be an individual project. You need to use Altera Quartus II to finish the handshaking protocol code using Verilog HDL. This project will allow students to learn how to design state machine using Verilog HDL for FPGA system and to understand the handshaking protocol that is used in various systems to transmit the data. Assignment In this assignment, you will learn how to develop a FPGA system using Altera Quartus II EDA software, and how to use ModelSim simulation system to verify your design. For this assignment, you should submit a paper to show your design, including the code with all necessary detailed tables, wave diagram(s), and descriptions. Descriptions Please read the EE-446_Embedded_Arch-FPGA_Project.pdf file, and download the source code. Prepare a Statechart Diagram. You need to write all detailed information in this diagram, such as triggers (events), list of actions (actions with event, or entry/do/exit actions in state), and any guards. Write a detailed description about your Statechart Diagram, as in your second homework assignment. According to your Statechart Diagram, complete the HS_Protocol.v code. Execute the ModelSim and capture the waveform for the hs_protocol module. The following signals should be included: CLK USB_WR, USB_RD, USB_RDYREQ, USB_ACK, USB_DONE, USB EMPTY CurrentState CODE_WR, CODE_RD, CODE_RDYREQ, CODE_ACK, CODE_EMPTY Identify the rising/falling edges in your handshaking protocol on your waveform. Include your completed source code for HS_Protocol.v as an appendix to your report.