Digital Logic Design Review-
Rationale
Various digital logic designs such as coat converters, decoders, encoders, comparators, multiplexors, adder-subtractors, multipliers, counters, registers, memory, and programmable logic such as PLA, PLD, ROM etc. are used as building blocks in the design of the central processing unit (cpu or processor) and special purpose processors (for input-output). A review of these building blocks which were presented to you in EECS 1100 Digital Logic Design class is essential for the comprehension of the subject matter for computer organization and architecture.
Questions-
1) Design a BCD to Excess-3 code converter.
2) Design a half adder
3) Design a full adder
4) Design a 4 bit adder; next revise your design to implement the rib: adder with carry look ahead.
5) Design a 4 bit subtractor, using the 4-bit adder: incorporate a control input to use the same circuit for either addition or subtraction.
6) Design a binary multiplier for two two-bit (unsigned) binary numbers: consider using the hale adder circuitry in your design.
7) Design a four-bit by three-bit binary multiplier: consider using the 4-bit binary adders in your design.
8) Design a four-bit magnitude comparator.
9) Design a three-to-eight line decoder.
10) Design a two-to-four Line decoder with enable input.
11) Design a 4x16 decoder constructed with two 3x8 decoders
12) Design a four input priority decoder.
13) Design a two-to-one line multiplexer.
14) Design a four-to-one line multiplexer.
15) Design a quadruple two-to-one line multiplexer.
16) Design a sequential circuit that detects a sequence of three or more consecutive 1's in a string of bits coming through an input line. Use D flip-flops.
17) Design a three-bit binary up-counter using T flip flops.
18) Design a four-bit register with clear and clock input using D flip-flops.
19) Enhance your four-bit register design with parallel load.
20) Design a four-bit shift register with D flip-flops.
21) Design a circuit to facilitate serial transfer of information from register A to register B using clock signal.
22) Design a multi-bit serial adder using shift registers, a single full adder and appropriate external logic.
23) Design a universal shift register with a clear control that clears the register to 0, a clock input to synch the operations, a shift right control, a shift left control, a parallel load control, n parallel output lines, and a control state that leaves the information in the register unchanged in response to the clock. Use 4x1 MUXs and D flip-flops to realize your design.
24) Design a four-bit binary ripple counter. Implement with T flip-flops. Next, implement with D flip-flops.
25) Design a four-bit BCD ripple counter with JK flip-flops. Design a three-decade BCD counter using the four-bit BCD ripple counters.
26) Design a four-bit synchronous binary counter. Implement with JK flip-flops.
27) Design four-bit synchronous binary up-down counter using T flip-flpos.
28) Design a four-bit synchronous binary counter with parallel load using JK flip flops.
29) Design a sequential circuit that will generate four timing signals that control the sequence of operations in a digital system using (a) shift register (configured as a ring counter), and (b) a counter with a decoder.
30) Design a basic memory cell with an SR flip-flops.
31) Design a 4x4 bit random access memory using your basic memory cell design in question 30.